1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a dynamic random access memory (DRAM) formed on an SOI (Silicon On Insulator) substrate.
2. Description of the Background Art
A semiconductor memory device is typically divided into a volatile memory such as a RAM, and a non-volatile memory such as a ROM. The volatile memory is further divided into a DRAM and a static random access memory (SRAM). The non-volatile memory includes a mask ROM, an EPROM, a flash memory, an EEPROM, a fuse ROM, and the like.
A DRAM has data stored by accumulating charge in the capacitor of a memory cell. Although such a DRAM requires a refresh operation, a DRAM having a large storage capacity can be manufactured at a low cost due to its simple structure of the memory cell.
Because data is stored by accumulating charge in a capacitor in a DRAM, the amount of charge stored in a capacitor is altered according to xcex1 particles emitted from its package or interconnection material. This change in the amount of charge will result in data inversion, i.e., soft error.
The demand for DRAMs having a higher integration density is also great. The potential of mass production is appreciable for DRAMs having a large storage capacity such as 256M bits and 1 G bits. Although the gate length is generally reduced to increase the integration density of a DRAM, this reduction in gate length has a limitation due to a significant short channel effect as the channel length is reduced.
In recent years, large scaled integrated circuits (LSI) are developed having circuit elements such as transistors formed on an SOI substrate with an insulation layer buried in the semiconductor substrate.
FIG. 92 is a plan view showing a structure of a MOS transistor formed on an SOI substrate. FIGS. 93 and 94 are sectional views of the MOS transistor shown in FIG. 92 taken along lines 93xe2x80x9493 and 94xe2x80x9494, respectively.
Referring to FIGS. 92-94, an MOS transistor includes an n+type source region 1, an n+type drain region 2, a p type body region 3, and a gate electrode 4. Body region 3 is located between source region 1 and drain region 2. When a predetermined potential is applied to gate electrode 4, a channel is formed in body region 3.
This MOS transistor is completely enclosed by a LOCOS oxide film 5 for isolation from an adjacent element. This MOS transistor is formed on an SOI substrate 6. SOI substrate 6 includes a silicon substrate 7, a buried oxide film 8 of SiO2, and an SOI active layer 9. Source region 1, drain region 2, and body region 3 are formed in this SOI active layer 9.
Body region 3 attains a floating state electrically since it is enclosed by LOCOS oxide film 5 and isolated from silicon substrate 7 by buried oxide layer 8. When body region 3 attains a floating state, the breakdown voltage between the source and drain becomes as low as approximately 3V due to a parasitic bipolar operation. There is also a possibility of a leakage current flow between the source and the drain. Furthermore, a body region 3 attaining a floating state induces the generation of a kink to disturb the drain current Id-drain voltage Vd characteristics. Therefore, the transistor cannot operate stably.
In view of the foregoing, a main object of the present invention is to provide a semiconductor memory device formed on an SOI substrate.
Another object of the present invention is to provide a DRAM with almost no generation of a soft error.
A further object of the present invention is to provide a DRAM having a greater storage capacity.
Still another object of the present invention is to further increase the data retaining time in a memory cell.
A still further object of the present invention is to improve the breakdown voltage between the source and drain of a MOS transistor in a semiconductor memory device.
Yet a further object of the present invention is to reduce leakage current between the source and drain of a MOS transistor in a semiconductor memory device.
Yet another object of the present invention is to operate a MOS transistor stably in a semiconductor memory device.
Yet a still further object of the present invention is to minimize increase in the layout area.
A semiconductor memory device according to an aspect of the present invention includes a plurality of N and P channel MOS semiconductor elements. The plurality of N and P channel MOS semiconductor elements are formed on an SOI substrate. Each MOS semiconductor element includes a source region, a drain region, and a body region located between the source and drain regions. At least one N channel MOS semiconductor element of the plurality of N channel MOS semiconductor elements has its body region electrically fixed. At least one P channel MOS semiconductor element of the plurality of P channel MOS semiconductor elements has its body region rendered floating electrically.
A semiconductor memory device according to another aspect of the present invention includes a plurality of N and P channel MOS semiconductor elements. The plurality of N and P channel MOS semiconductor elements are formed on an SOI substrate. Each MOS semiconductor element includes a source region, a drain region, and a body region located between the source and drain regions. Any body region of the plurality of N channel MOS semiconductor elements is fixed electrically. All the body regions of the plurality of P channel MOS semiconductor elements are rendered floating electrically.
A semiconductor memory device according to a further aspect of the present invention includes a plurality of N and P channel MOS semiconductor elements. The plurality of N and P channel MOS semiconductor elements are formed on an SOI substrate. Each MOS semiconductor element includes a source region, a drain region and a body region located between the source and drain regions. All the body regions of the plurality of N channel MOS semiconductor devices are fixed electrically. All the body regions of the plurality of P channel MOS semiconductor elements are rendered floating.
A semiconductor memory device according to still another aspect of the present invention includes a plurality of MOS capacitors. The plurality of MOS capacitors are formed on an SOI substrate. Each MOS capacitor includes a source region, a drain region connected to the source region, and a body region located between the source and drain regions. At least one MOS capacitor of the plurality of MOS capacitors has its body region connected to its own source region.
A semiconductor memory device according to still a further aspect of the present invention includes a plurality of MOS transistors and a plurality of bit line pairs for storing data. The stored data is read out via a bit line pair. The plurality of MOS transistors and the plurality of bit line pairs are formed on an SOI substrate. Each MOS transistor includes a source region, a drain region, and a body region located therebetween. The body region of a MOS transistor out of the plurality of MOS transistors having a source region or a drain region connected to any of the plurality of bit line pairs is electrically fixed.
A semiconductor memory device according to yet a further aspect of the present invention includes a plurality of MOS transistors. The plurality of MOS transistors are formed on an SOI substrate. Each MOS transistor includes a source region, a drain region, and a body region located therebetween. A variable potential is supplied to the body region of at least one of the plurality of MOS transistors. This variable potential is the reverse voltage wits respect to the PN junction between one of the source and drain regions and the body region. Preferably, the body region of the at least one MOS transistor is connected to its own source region.
A semiconductor memory device according to yet another aspect of the present invention includes a plurality of bit line pairs, and a plurality of sense amplifiers. The plurality of sense amplifiers are provided corresponding to the plurality of bit line pairs. Each sense amplifier amplifies the potential difference between a corresponding bit line pair. The plurality of bit line pairs and the plurality of sense amplifiers are formed on an SOI substrate. Each sense amplifier includes first and second N channel MOS transistors connected in series between the corresponding bit line pair. The body region of the first N channel MOS transistor located between the source region and the drain region is connected to its own source region. The body region of the second N channel MOS transistor located between the source region and the drain region is connected to its own source region.
Preferably, each sense amplifier further includes first and second P channel MOS transistors connected in series between a corresponding bit line pair. The body region of the first P channel MOS transistor located between the source region and the drain region is connected to its own source region. The body region of the second P channel MOS transistor located between the source region and the drain region is connected to its own source region.
A semiconductor memory device according to yet a still further aspect of the present invention includes a plurality of MOS transistors and output terminals for storing data. The stored data is externally output via the output terminal. The plurality of MOS transistors are formed on an SOI substrate. Each MOS transistor includes a source region, a drain region, and a body region located therebetween. Out of the plurality of the MOS transistors, the body region of the MOS transistor having the source region connected to the output terminal is connected to its own source region.
A semiconductor memory device according to a further aspect of the present invention includes a plurality of MOS transistors. A predetermined power supply voltage is supplied to the semiconductor memory device. The plurality of MOS transistors are formed on an SIO substrate. Out of the plurality of the MOS transistors, the body region of the MOS transistor having a voltage higher than the power supply voltage supplied between the source region and the drain region is electrically fixed.
A semiconductor memory device according to a further aspect of the present invention includes a plurality of MOS transistors. The plurality of MOS transistors are formed on an SOI substrate. Out of the plurality of MOS transistors, the body region located between the source region and the drain region of a MOS transistor carrying out an analog operation is electrically fixed. Preferably, the MOS transistor that carries out an analog operation is a MOS transistor in a circuit that processes a signal of an amplitude smaller than that of power supply voltage supplied to the semiconductor memory device.
A semiconductor memory device according to a further aspect of the present invention includes a plurality of MOS transistors and input/output lines for storing data. The stored data is read/written via the input/output line. The plurality of MOS transistors and the input/output lines are formed on an SOI substrate. Each MOS transistor includes a source region, a drain region, and a body region located therebetween. Out of the plurality of MOS transistors, the body region of a MOS transistor having the source region or the drain region connected to the input/output line is electrically fixed.
A semiconductor memory device according to a further aspect of the present invention includes a plurality of MOS transistors. The plurality of MOS transistors are formed on an SOI substrate. Out of the plurality of MOS transistors, the body region located between the source and drain region of the MOS transistor in the input stage receiving an externally applied signal is electrically fixed.
A semiconductor memory device according to a further aspect of the present invention includes a plurality of MOS transistors. The plurality of MOS transistors are formed on an SOI substrate. Out of the plurality of MOS transistors, the body region located between the source and drain regions of the MOS transistor at an output stage for outputting a signal is electrically fixed.
A semiconductor memory device according to a further aspect of the present invention includes a plurality of MOS transistors. Any N channel MOS transistors out of the plurality of MOS transistors are connected in series between an output node for providing a signal and a ground node. The plurality of MOS transistors are formed on an SOI substrate. Out of the any of the N channel MOS transistors, the body region located between the source region and the drain region of at least one N channel MOS transistors that does not have a source region directly connected to the ground node is electrically fixed.
A semiconductor memory device according to a further aspect of the present invention includes a plurality of MOS transistors. The plurality of MOS transistors are formed on an SOI substrate. Out of the plurality of MOS transistors, the body region located between the source region and the drain region of a MOS transistor having a gate length shorter than a predetermined gate length is electrically fixed. Out of the plurality of MOS transistors, the body region located between the source region and the drain region of a MOS transistor having a gate length longer than the predetermined gate length is rendered floating electrically.
A semiconductor memory device according to a further aspect of the present invention includes a plurality of first and second conductive channel type MOS transistors. The plurality of first and second conductive channel type MOS transistors are formed on an SOI substrate. At least one first conductive channel type MOS transistor of the plurality of first conductive channel type MOS transistors has a first threshold voltage. At least one first conductive channel MOS transistor of the plurality of first conductive channel MOS transistors has a second threshold voltage differing from the first threshold voltage.
A semiconductor memory device according to a further aspect of the present invention includes a plurality of first and second conductive channel type MOS transistors. The plurality of first and second conductive channel type MOS transistors are formed on an SOI substrate. A second conductivity type body region located between a first conductivity type source region and a first conductivity type drain region of at least one first conductive channel MOS transistor of the plurality of first conductive channel type MOS transistors includes a conductive layer having a first impurity concentration on the surface thereof. A second conductivity type body region located between the first conductivity type source region and the first conductivity type drain region between at least another first conductive channel type MOS transistor of the plurality of first conductive channel type MOS transistors includes a conductive layer having a second impurity concentration differing from the first impurity concentration at the surface thereof.
A semiconductor memory device according to a further aspect of the present invention includes a plurality of first and second conductive channel type MOS transistors. The plurality of first and second conductive channel type MOS transistors are formed on an SOI substrate. A second conductivity type body region located between a first conductivity type source region and the first conductivity type drain region of at least one first conductive channel type MOS transistor out of the plurality of first conductive channel type MOS transistors receives a first potential. A second conductivity type body region located between the first conductivity type source region and the first conductivity type drain region of at least another first conductive channel type MOS transistor out of the plurality of first conductive channel type MOS transistors receives a second potential differing from the first potential.
A semiconductor memory device according to a further aspect of the present invention includes a memory cell array of a plurality of first MOS transistors, and a peripheral circuit of a plurality of second MOS transistors. The plurality of first and second MOS transistors are formed on an SOI substrate. The plurality of first MOS transistors have a threshold voltage higher than that of the plurality of second MOS transistors.
A semiconductor-memory device according to a further aspect of the present invention includes a plurality of MOS semiconductor elements. The plurality of MOS semiconductor elements are formed on an SOI substrate. The source and drain regions of any MOS semiconductor elements out of the plurality of MOS semiconductor elements are brought into contact with an insulation layer in the SOI substrate.
A semiconductor memory device according to a further aspect of the present invention includes a memory cell array of a plurality of first MOS transistors, and a peripheral circuit of a plurality of second MOS transistors. The memory cell array and the peripheral circuit are formed on an SOI substrate. The source and drain regions of the plurality of first MOS transistors are brought into contact with an insulation layer of the SOI substrate.
A semiconductor memory device according to a further aspect of the present invention includes at least one first semiconductor element and at least one second semiconductor element. An element isolation film for isolating the first and second semiconductor elements are formed on an SOI substrate. The element isolation film is brought into contact with an insulation layer in the SOI substrate.
A semiconductor memory device according to a further aspect of the present invention is formed on an SOI substrate. The SOI substrate includes a semiconductor substrate, a buried insulation layer formed on the semiconductor substrate, and a semiconductor active layer formed on the buried insulation layer. The semiconductor memory device further includes a supply circuit. The supply circuit supplies a predetermined substrate potential to the semiconductor substrate of the SOI substrate.
Because the above-described semiconductor memory device in which all semiconductor elements are formed on an SOI substrate has the body region of at least one N channel MOS semiconductor element electrically fixed, leakage current between the source and drain is reduced and the breakdown voltage between the source and drain is increased. Because there is almost no kinks in the fixed body region, a stable Id-Vd characteristic can be obtained. Furthermore, because the body region of at least one P channel MOS semiconductor element is rendered floating electrically, wiring for fixing the body region is not required, and increase of the layout area is minimized. In general, the breakdown voltage between the source and drain in an N channel MOS semiconductor element is smaller than that of the P channel MOS semiconductor element. Here, the body region of an N channel MOS transistor is fixed, so that the breakdown voltage between the source and drain thereof is similar to that of a P channel MOS semiconductor element.
Because the body region of a MOS capacitor is connected to its own source region, the body region thereof is fixed. Therefore, this MOS capacitor can operate stably. Furthermore, because the body region is connected to the source region, wiring for supplying potential to the body region is not required. Thus, there is almost no increase in the layout area.
Because the body region of the MOS transistor connected to the bit line pair is fixed, leakage current flowing from the bit line pair via the MOS transistor, or the leakage current flowing to the bit line pair via the MOS transistor is reduced.
Because a variable potential is applied to the body region of a MOS transistor that becomes a reverse voltage with respect to the PN junction formed of the body region and the source/drain region, the transistor does not carry out bipolar operation, and body effect does not occur. Therefore, this MOS transistor operates stably.
Because the body region of the MOS transistor to which high voltage is applied between the source and drain is fixed, the breakdown voltage between the source and drain is increased, so that this transistor will operate properly even when high voltage is applied between the source and drain.
Because the body region of a MOS transistor carrying out an analog operation is fixed, there is almost no kinks in that transistor. Therefore, this transistor always operates stably.
Because the body region of a MOS transistor having source/drain regions connected to an input/output line is fixed, a great leakage current will not flow between the source and drain, so that accurate data can be input and output.
Because the body region of a MOS transistor at an input stage is fixed, a great leakage current will not flow between the source and drain, so that a desired input impedance can be obtained.
Because the body region of a MOS transistor at an output stage is fixed, a great amount of leakage current will not flow between the source and drain, so that a desired output impedance can be obtained.
Because the body region of an N channel MOS transistor that is not directly connected to a ground node is fixed, the threshold voltage of the transistor including that fixed body region is reduced, whereby the transistor operates more speedily. Therefore, those transistor can operate properly even when the power supply voltage is low.
Because the body region of a MOS transistor having a short gate length is fixed, the breakdown voltage between the source and drain of that transistor is equal to that of a transistor having a greater gate length. Also, the level of the leakage current flowing between the source and drain of the transistor of the short gate length is similar to that of the transistor of the long gate length. Furthermore, because the body region of the MOS transistor of the long gate length is rendered floating, wiring for providing potential to the body region is not required, so that increase in the layout area can be suppressed to a minimum.
Because transistors of the same conductivity type have more than one type of threshold voltage, these transistors operate stably.
The junction capacitance of the source/drain region is reduced since a semiconductor element is formed in the thin SOI active layer.
Because an element isolation film such as a Locos oxide film is formed in a thin SOI active layer, the element isolation film comes into contact with the insulation layer of the SOI substrate.
Because a predetermined substrate potential is supplied to the semiconductor substrate of an SOI substrate, the semiconductor substrate is electrically fixed. Therefore, the potential of the semiconductor substrate will not change, so that change in the potential of the semiconductor active layer will also not occur. As a result, semiconductor elements such as a transistor formed on the semiconductor active layer operates stably.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.